Designing a radio receiver using conventional architectures in integrated circuit fabrication technologies with feature sizes of 65 nm and less presents substantial challenges. These challenges include limited dynamic range due to low supply voltage, low intrinsic voltage gain from transistors, high flicker noise corner, difficulty in cascoding transistors due to headroom issues, and the general squirrely behavior of field effect transistors (FETs) in these processes.
A need therefore exists for improved radio receiver architectures that can provide high performance even in fabrication technologies with small feature sizes.